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dc.contributor.authorElsalahati, Tamer
dc.date.accessioned2017-12-15T13:38:38Z
dc.date.available2017-12-15T13:38:38Z
dc.identifier.urihttp://hdl.handle.net/10222/73527
dc.description.abstractA design technique for an asynchronous Analog-to-Digital Converter (ADC) is presented. The proposed design retains a clockless level crossing sampling technique, and then applies a Wavelet Neural Network (WNN) technique. High-level simulation results are shown for various ADC resolutions. The Signal to Noise and Distortion Ratio (SNDR) achieved for 4-bit ADC systems are presented. It has been shown that a 4-bit system with the proposed asynchronous ADC architecture using a WNN technique achieves an Effective Number Of Bits (ENOB) of up to 38 bits depending on the input frequency and resolution.en_US
dc.language.isoen_USen_US
dc.subjectQuantization (signal)en_US
dc.subjectNeural networksen_US
dc.subjectWavelet transformsen_US
dc.subjectDelta modulationen_US
dc.subjectSignal resolutionen_US
dc.subjectWavelet Neural Networksen_US
dc.subjectContinuous Timeen_US
dc.subjectClockless ADCen_US
dc.subjectLevel Crossing ADCen_US
dc.titleHigh Precision Clock-Less ADC Using Wavelet Neural Networksen_US
dc.typeThesisen_US
dc.date.defence2017-12-05
dc.contributor.departmentDepartment of Electrical & Computer Engineeringen_US
dc.contributor.degreeMaster of Applied Scienceen_US
dc.contributor.external-examinerNAen_US
dc.contributor.graduate-coordinatorDr. Jason Guen_US
dc.contributor.thesis-readerDr. William Phillipsen_US
dc.contributor.thesis-readerDr. Jason Guen_US
dc.contributor.thesis-supervisorDr. E. El-Masryen_US
dc.contributor.ethics-approvalNot Applicableen_US
dc.contributor.manuscriptsNot Applicableen_US
dc.contributor.copyright-releaseYesen_US
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